Chip on Wafer on Substrate 結果共2筆

《路透社》報導，兩名知情人士透露，晶片大廠台積電（TSMC）擬在日本建立先進封裝產能。其中一個選項是將獨家的CoWoS（Chip on Wafer on Substrate）封裝技術導入日本，目前台積電的CoWoS產能都在台灣。據報導，隨著AI晶片需求急遽增加，台積電先進封裝產能吃緊，因此將聚集製造裝備與材料製造商的日本列為候選地點。

Taiwan Semiconductor Manufacturing Company (TSMC) predicts a surge in artificial intelligence (AI) orders in the coming year, with October’s revenue reaching NT$243.203 billion ($8.6 billion), a 34.8 percent monthly increase and a 15.7 percent annual increase. TSMC’s stock price has also been on a steady rise, accumulating a growth of 7.5 percent since November. Morgan Stanley semiconductor research analyst Charlie Chan attributes TSMC’s revenue growth to signs of recovery and the robust demand for AI semiconductors worldwide. NVIDIA’s expanded order to TSMC, along with increased demand from clients like Apple and Advanced Micro Devices (AMD), has led TSMC to accelerate the enhancement of its advanced packaging technology, Chip on Wafer on Substrate (CoWoS). CoWoS enables TSMC to effectively reduce costs and trim electric consumption by packaging chiplets on a silicon interposer and placing them on a package substrate. However, TSMC’s current CoWoS capacity remains a bottleneck for NVIDIA’s AI GPU chips, though the company forecasts a rebound in productivity by the end of 2024 to meet customer demand.